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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os evaluation kit available general description the max7325 2-wire serial-interfaced peripheral features 16 i/o ports. ports are divided into eight push-pull out- puts and eight i/os with selectable internal pullups and transition detection. eight ports are push-pull outputs and eight i/os may be used as a logic input or an open- drain output. ports are overvoltage protected to +6v. all i/o ports configured as inputs are continuously mon- itored for state changes (transition detection). state changes are indicated by the int output. the interrupt is latched, allowing detection of transient changes. when the max7325 is subsequently accessed through the serial interface, any pending interrupt is cleared. the open-drain outputs are rated to sink 20ma, and are capable of driving leds. the rst input clears the serial interface, terminating any i 2 c communication to or from the max7325. the max7325 uses two address inputs with four-level logic to allow 16 i 2 c slave addresses. the slave address also determines the power-up logic state for the i/o ports, and enables or disables internal 40k ? pullups in groups of four ports. the max7325 is one device in a family of pin-compatible port expanders with a choice of input ports, open-drain i/o ports, and push-pull output ports (see table 1). the max7325 is available in 24-pin qsop and tqfn packages and is specified over the -40? to +125? automotive temperature range. applications cell phones notebooks san/nas satellite radio servers automotive features 400khz i 2 c serial interface +1.71v to +5.5v operation 8 push-pull outputs 8 open-drain i/o ports, rated to 20ma sink current i/o ports are overvoltage protected to +6v selectable i/o port power-up default logic states transient changes are latched, allowing detection between read operations int output alerts change on inputs ad0 and ad2 inputs select from 16 slave addresses low 0.6? (typ) standby current -40? to +125? temperature range 19-3807; rev 1; 9/12 ordering information part temp range pin-package max7325aeg+ -40? to +125? 24 qsop max7325aeg/v+ -40? to +125? 24 qsop max7325atg+ -40? to +125? 24 tqfn-ep* (4mm x 4mm) typical application circuit and functional diagram appear at end of data sheet. selector guide part inputs interrupt mask open- drain outputs push-pull outputs max7324 8 yes 8 max7325 up to 8 up to 8 8 max7326 4 yes 12 max7327 up to 4 up to 4 12 + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed paddle. /v denotes an automotive qualified part. tqfn (4mm x 4mm) + top view max7325 19 20 21 22 12 3456 18 17 16 15 14 13 23 24 12 11 10 9 8 7 scl v+ sda int ad2 p0 p1 p2 p3 p4 p5 ad0 o15 o13 o12 o11 rst o10 o8 o9 gnd p6 p7 o14 exposed paddle pin configurations pin configurations continued at end of data sheet.
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 2 maxim integrated absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) supply voltage v+....................................................-0.3v to +6v scl, sda, ad0, ad2, rst , int , p0?7 ...................-0.3v to +6v o8?15 ........................................................-0.3v to (v+ + 0.3v) o8?15 output current ...................................................?5ma p0?7 sink current ......................................................................25ma sda sink current ........................................................................ 10ma int sink current..................................................................10ma total v+ current..................................................................50ma total gnd current ...........................................................100ma continuous power dissipation (t a = +70?) 24-pin qsop (derate 9.5mw/? over +70?)...........761.9mw 24-pin tqfn (derate 20.8mw/? over+70?) ........1666.7mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? dc electrical characteristics (v+ = +1.71v to +5.5v, t a = -40? to +125?, unless otherwise noted. typical values are at v+ = +3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ t a = -40? to +125? 1.71 5.50 v power-on-reset voltage v por v+ falling 1.6 v standby current (interface idle) i stb scl and sda and other digital inputs at v+ t a = -40? to +125? 0.6 1.9 ? supply current (interface running) i+ f scl = 400khz; other digital inputs at v+ t a = -40? to +125? 23 55 ? v+ < 1.8v 0.8 x v+ input high-voltage sda, scl, ad0, ad2, rst , p0?7 v ih v+ 1.8v 0.7 x v+ v v+ < 1.8v 0.2 x v+ input low-voltage sda, scl, ad0, ad2, rst , p0?7 v il v+ 1.8v 0.3 x v+ v input leakage current sda, scl, ad0, ad2, rst , p0?7 i ih , i il sda, scl, ad0, ad2, rst , p0?7 at v+ or gnd, internal pullup disabled -0.2 +0.2 a input capacitance sda, scl, ad0, ad2, rst , p0?7 10 pf v+ = +1.71v, i sink = 5ma (qsop) 90 180 v+ = +1.71v, i sink = 5ma (tqfn) 90 230 v+ = +2.5v, i sink = 10ma (qsop) 110 210 v+ = +2.5v, i sink = 10ma (tqfn) 110 260 v+ = +3.3v, i sink = 15ma (qsop) 130 230 v+ = +3.3v, i sink = 15ma (tqfn) 130 280 v+ = +5v, i sink = 20ma (qsop) 140 250 output low voltage o8?15, p0?7 v ol v+ = +5v, i sink = 20ma (tqfn) 140 300 mv v+ = +1.71v, i source = 2ma v + - 250 v + - 30 v+ = +2.5v, i source = 5ma v + - 360 v + - 70 v+ = +3.3v, i source = 5ma v + - 260 v + - 100 output high voltage o8?15 v oh v+ = +5v, i source = 10ma v + - 360 v + - 120 mv output low-voltage sda v olsda i sink = 6ma 250 mv output low-voltage int v olint i sink = 5ma 130 250 mv port input pullup resistor r pu 25 40 55 k ?
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 3 maxim integrated port and interrupt int timing characteristics (v+ = +1.71v to +5.5v, t a = -40? to +125?, unless otherwise noted. typical values are at v+ = +3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units port output data valid t ppv c l 100pf 4 s port input setup time t psu c l 100pf 0 s port input hold time t ph c l 100pf 4 s int input data valid time t iv c l 100pf 4 s int reset delay time from stop t ip c l 100pf 4 s int reset delay time from acknowledge t ir c l 100pf 4 s timing characteristics (v+ = +1.71v to +5.5v, t a = -40? to +125?, unless otherwise noted. typical values are at v+ = +3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units serial-clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 2) 0.9 ? data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and scl signals, receiving t r (notes 3, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 3, 4) 20 + 0.1c b 300 ns fall time of sda transmitting t f,tx (notes 3, 4) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 5) 50 ns capacitive load for each bus line c b (note 3) 400 pf rst pulse width t w 500 ns rst rising to start condition setup time t rst 1s note 1: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) in order to bridge the undefined region of scl? falling edge. note 3: guaranteed by design. note 4: c b = total capacitance of one bus line in pf. i sink 6ma. t r and t f measured between 0.3 x v+ and 0.7 x v+. note 5: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
standby current vs. temperature temperature ( c) standby current ( a) max7325 toc01 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v+ = +3.3v v+ = +5.0v v+ = +2.5v v+ = +1.71v f scl = 0khz supply current vs. temperature temperature ( c) supply current ( a) max7325 toc02 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 10 20 30 40 50 60 v+ = +3.3v v+ = +5.0v v+ = +2.5v v+ = +1.71v f scl = 400khz 4 maxim integrated max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os output voltage low vs. temperature temperature ( c) output voltage low (v) max7325 toc03 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0.05 0.10 0.15 0.20 0.25 v+ = +3.3v i sink = 15ma v+ = +5.0v i sink = 20ma v+ = +2.5v i sink = 10ma v+ = +1.71v i sink = 5ma output voltage high vs. temperature temperature ( c) output voltage high (v) max7325 toc04 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1 2 3 4 5 6 v+ = +3.3v i source = 5ma v+ = +5.0v i source = 10ma v+ = +2.5v i source = 5ma v+ = +1.71v i source = 2ma pin description pin qsop tqfn name function 122 int interrupt output, active low. int is an open-drain output. 223 rst reset input, active low. drive rst low to clear the 2-wire interface. 3, 21 24, 18 ad2, ad0 address inputs. select device slave address with ad0 and ad2. connect ad0 and ad2 to either gnd, v+, scl, or sda to give four logic combinations (see tables 2 and 3). 4?1 1? p0?7 open-drain i/o ports 12 9 gnd ground 13?0 10?7 o8?15 output ports. o8?15 are push-pull outputs rated at 20ma. 22 19 scl i 2 c-compatible serial-clock input 23 20 sda i 2 c-compatible serial-data i/o 24 21 v+ positive supply voltage. bypass v+ to gnd with a ceramic capacitor of at least 0.047?. ep exposed paddle (tqfn only). connect exposed pad to gnd. typical operating characteristics (t a = +25?, unless otherwise noted.)
detailed description max7319?ax7329 family comparison the max7324?ax7327 family consists of four pin- compatible, 16-port expanders that integrate the func- tions of the max7320 and one of either max7319, max7321, max7322, or max7323. functional overview the max7325 is a general-purpose port expander oper- ating from a +1.71v to +5.5v supply with eight push-pull outputs and eight open-drain i/o ports. each open-drain output is rated to sink 20ma, and the entire device is rated to sink 100ma into all ports combined. the outputs drive loads connected to supplies up to +5.5v. the max7325 is set to two of 32 i 2 c slave addresses (see tables 2 and 3) using the address select inputs ad0 and ad2, and is accessed over an i 2 c serial inter- face up to 400khz. the eight outputs and eight i/os have different slave addresses. the eight push-pull out- puts have the 101xxxx addresses and the eight inputs have addresses with 110xxxx. the rst input clears the serial interface in case of a bus lockup, terminating any serial transaction to or from the max7325. configure any port as a logic input by setting the port output logic-high (logic-high for an open-drain output is high impedance). when the max7325 is read through the serial interface, the actual logic levels at the ports are read back. max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 5 maxim integrated part i 2 c slave address inputs input interrupt mask open- drain outputs push- pull outputs configuration 16-port expanders max7324 8 yes 8 8 input and 8 push-pull output versions: 8 input ports with programmable latching transition detection interrupt and selectable pullups. 8 push-pull outputs with selectable default logic levels. offers maximum versatility for automatic input monitoring. an interrupt mask selects which inputs cause an interrupt on transitions, and transition flags identify which inputs have changed (even if only for a transient) since the ports were last read. max7325 101xxxx and 110xxxx up to 8 up to 8 8 8 i/o and 8 push-pull output versions: 8 open-drain i/o ports with latching transition detection interrupt and selectable pullups. 8 push-pull outputs with selectable default logic levels. open-drain outputs can level shift the logic-high state to a higher or lower voltage than v+ using external pullup resistors, but pullups draw current when output is low. any open-drain port can be used as an input by setting the open-drain output to logic- high. transition flags identify which open-drain port inputs have changed (even if only for a transient) since the ports were last read. table 1. max7319?ax7329 family comparison
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 6 maxim integrated part i 2 c slave address inputs input interrupt mask open- drain outputs push- pull outputs configuration max7326 4 yes 12 4 input-only, 12 push-pull output versions: 4 input ports with programmable latching transition detection interrupt and selectable pullups. 12 push-pull outputs with selectable default logic levels. offers maximum versatility for automatic input monitoring. an interrupt mask selects which inputs cause an interrupt on transitions, and transition flags identify which inputs have changed (even if only for a transient) since the ports were last read. max7327 101xxxx and 110xxxx up to 4 up to 4 12 4 i/o, 12 push-pull output versions: 4 open-drain i/o ports with latching transition detection interrupt and selectable pullups. 12 push-pull outputs with selectable default logic levels. open-drain outputs can level shift the logic-high state to a higher or lower voltage than v+ using external pullup resistors, but pullups draw current when output is low. any open-drain port can be used as an input by setting the open-drain output to logic- high. transition flags identify which open-drain port inputs have changed (even if only for a transient) since the ports were last read. 8-port expanders max7319 110xxxx 8 yes input-only versions: 8 input ports with programmable latching transition detection interrupt and selectable pullups. max7320 101xxxx 8 output-only versions: 8 push-pull outputs with selectable power-up default levels. max7321 110xxxx up to 8 up to 8 i/o versions: 8 open-drain i/o ports with latching transition detection interrupt and selectable pullups. max7322 110xxxx 4 yes 4 4 input-only, 4 output-only versions: 4 input ports with programmable latching transition detection interrupt and selectable pullups. 4 push-pull outputs with selectable power-up default levels. table 1. max7319?ax7329 family comparison (continued)
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 7 maxim integrated the open-drain ports offer latching transition detection when used as inputs. all input ports are continuously monitored for changes. an input change sets one of 8 flag bits that identify changed input(s). all flags are cleared upon a subsequent read or write transaction to the max7325. a latching interrupt output, int , is programmed to flag logic changes on ports used as inputs. data changes on any input port forces int to a logic-low. changing the i/o port level through the serial interface does not cause an interrupt. the interrupt output int is deassert- ed when the max7325 is next accessed through the serial interface. internal pullup resistors to v+ are selected by the address select inputs, ad0 and ad2. pullups are enabled on the input ports in groups of four (see table 2). use the slave address selection to ensure that i/o ports used as inputs are logic-high on power-up. i/o ports with internal pullups enabled default to a logic-high out- put state. i/o ports with internal pullups disabled default to a logic-low output state. output port power-up logic levels are selected by the address select inputs, ad0 and ad2. ports default to logic-high or logic-low on power-up in groups of four (see tables 2 and 3). initial power-up on power-up, the transition detection logic is reset, and int is deasserted. the transition flags are cleared to indi- cate no data changes. the power-up default states of the 16 i/o ports are set according to the i 2 c slave address selection inputs, ad0 and ad2 (tables 2 and 3). for i/o ports used as inputs, ensure that the default states are logic-high so that the i/o ports power up in the high- impedance state. all i/o ports configured with pullups enabled also have a logic-high power-up state. power-on reset the max7325 contains an integral power-on-reset (por) circuit that ensures all registers are reset to a known state on power-up. when v+ rises above v por (1.6v max), the por circuit releases the registers and 2-wire interface for normal operation. when v+ drops to less than v por , the max7325 resets all register con- tents to the por defaults (tables 2 and 3). rst input the active-low rst input voids any i 2 c transaction involving the max7325, forcing the max7325 into the i 2 c stop condition. a reset does not affect the inter- rupt output ( int ). standby mode when the serial interface is idle, the max7325 automatical- ly enters standby mode, drawing minimal supply current. slave address, power-up default logic levels, and input pullup selection address inputs ad0 and ad2 determine the max7325 slave address, set the power-up i/o state for the ports, and select which inputs have pullup resistors. internal pullups and power-up default states are set in groups of four (see table 2). the max7325 slave address is determined on each i 2 c transmission, regardless of whether the transmission is actually addressing the max7325. the max7325 distin- guishes whether address inputs ad0 and ad2 are con- nected to sda or scl instead of fixed logic levels v+ or gnd during this transmission. the max7325 slave address can be configured dynamically in the applica- tion without cycling the device supply. on initial power-up, the max7325 cannot decode the address inputs ad0 and ad2 fully until the first i 2 c transmission. ad0 and ad2 initially appear to be part i 2 c slave address inputs input interrupt mask open- drain outputs push- pull outputs configuration max7323 110xxxx up to 4 up to 4 4 4 i/o, 4 output-only versions: 4 open-drain i/o ports with latching transition detection interrupt and selectable pullups. 4 push-pull outputs with selectable power-up default levels. max7328 max7329 0100xxx 0111xxx up to 8 up to 8 8 open-drain i/o ports with nonlatching transition detection interrupt and pullups on all ports. table 1. max7319?ax7329 family comparison (continued)
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 8 maxim integrated connected to v+ or gnd. this is important because the address selection is used to determine the power-up logic state and whether pullups are enabled. at power- up, the i 2 c sda and scl bus interface lines are high impedance at the inputs of every device (master or slave) connected to the bus, including the max7325. this is guaranteed as part of the i 2 c specification. therefore, when address inputs ad0 and ad2 are con- nected to sda or scl during power-up, they appear to be connected to v+. the power-up logic uses ad0 to select the power-up state and whether pullups are enabled for ports p0?3, and ad2 for ports p4?7. the rule is that a logic-high, sda, or scl connection selects the pullups and sets the default logic state to high. a logic-low deselects the pullups and sets the default logic state to low (table 2). the port configuration is correct on power-up for a standard i 2 c configuration, where sda or scl are pulled up to v+ by the external i 2 c pullup resistors. there are circumstances where the assumption that sda = scl = v+ on power-up is not true?or example, in applications in which there is legitimate bus activity during power-up. if sda and scl are terminated with pullup resistors to a different supply voltage than the max7325? supply voltage, and if that pullup supply rises later than the max7325? supply, then sda or scl may appear at power-up to be connected to gnd. in such applications, use the four address combina- tions that are selected by connecting address inputs ad0 and ad2 to v+ or gnd (shown in bold in tables 2 and 3). these selections are guaranteed to be correct at power-up, independent of sda and scl behavior. if one of the other 12 address combinations is used, an unexpected combination of pullups might be asserted until the first i 2 c transmission (to any device, not neces- sarily the max7325) is put on the bus, and an unex- pected combination of ports can initialize as logic-low outputs instead of inputs or logic-high outputs. pin connection device address port power-up default 40k ? input pullups enabled ad2 ad0 a6a5a4a3a2a1a0p7p6p5p4p3p2p1p0p7p6p5p4p3p2p1p0 scl gnd110000011110000 yyyy scl v+ 110000111111111 yyyyyyyy scl scl110001011111111 yyyyyyyy scl sda110001111111111 yyyyyyyy sdagnd110010011110000 yyyy sda v+ 110010111111111 yyyyyyyy sda scl110011011111111 yyyyyyyy sda sda110011111111111 yyyyyyyy gndgnd110100000000000 gnd v+ 110100100001111 yyyy gnd scl110101000001111 yyyy gndsda110101100001111 yyyy v+ gnd110110011110000yyyy v+ v+ 110110111111111yyy yyyyy v+ scl110111011111111 yyyyyyyy v+ sda110111111111111 yyyyyyyy table 2. max7325 address map for ports p0?7
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 9 maxim integrated pin c o nn ec tio n device address outputs power-up default ad2 ad0 a6 a5 a4 a3 a2 a1 a0 o15 o14 o13 o12 o11 o10 o9 o8 sclgnd101000011110000 sclv+101000111111111 sclscl101001011111111 sclsda101001111111111 sdagnd101010011110000 sdav+101010111111111 sdascl101011011111111 sdasda101011111111111 gndgnd101100000000000 gndv+101100100001111 gndscl101101000001111 gndsda101101100001111 v+gnd101110011110000 v+v+101110111111111 v+scl101111011111111 v+sda101111111111111 table 3. max7325 address map for outputs o8?15 port inputs i/o port inputs switch at the cmos-logic levels as determined by the expander? supply voltage, and are overvoltage tolerant to +6v, independent of the expander? supply voltage. i/o port input transition detection all i/o ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. the state of the ports is stored in an internal ?napshot?register for transition monitoring. the snapshot is continuously compared with the actual input conditions, and if a change is detected for any port input, int is asserted to signal a state change. the input ports are sampled (internally latched into the snapshot register) and the old transition flags cleared during the i 2 c acknowl- edge of every max7325 read and write access. the previ- ous port transition flags are read through the serial interface as the second byte of a 2-byte read sequence.
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 10 maxim integrated serial interface serial addressing the max7325 operates as a slave that sends and receives data through an i 2 c interface. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between mas- ter(s) and slave(s). the master initiates all data transfers to and from the max7325 and generates the scl clock that synchronizes the data transfer (figure 1). sda operates as both an input and an open-drain out- put. a pullup resistor, typically 4.7k ? , is required on sda. scl operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire interface, or if the master in a sin- gle-master system has an open-drain scl output. each transmission consists of a start condition sent by a master, followed by the max7325? 7-bit slave addresses plus r/ w bits, 1 or more data bytes, and finally a stop condition (figure 2). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 2). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 3). scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta figure 1. 2-wire serial interface timing details sda scl start condition stop condition sp figure 2. start and stop conditions sda scl data line stable; data valid change of data allowed figure 3. bit transfer
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 11 maxim integrated acknowledge the acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data (figure 4). each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the max7325, the device generates the acknowledge bit because the max7325 is the recipi- ent. when the max7325 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave address each max7325 has two different 7-bit slave addresses (tables 2 and 3). the addresses are different to communi- cate to either the eight push-pull outputs or the eight i/os. the 8th bit of the slave address following the 7-bit slave address is the r/ w bit. it is low for a write command, and high for a read command (figure 5). the first (a6), sec- ond (a5), and third (a4) bits of the max7325 slave address are always 1, 1, and 0 (p0?7) or 1, 0, and 1 (o8 to o15). connect ad0 and ad2 to gnd, v +, sda, or scl to select the slave address bits a3, a2, a1, and a0. the max7325 has 16 possible pairs of slave addresses (tables 2 and 3), allowing up to 16 max7325 devices on an i 2 c bus. accessing the max7325 the max7325 is accessed though an i 2 c interface. the max7325 has two different 7-bit slave addresses for either the eight open-drain i/o ports (p0?7) or the eight push-pull ports (o8?15). see tables 2 and 3. a single-byte read from the i/o ports (p0?7) of the max7325 returns the status of the eight i/o ports and clears both the internal transition flags and the int out- put when the master acknowledges the slave address byte. a single-byte read from the eight push-pull ports (o8?15) returns the status of the eight output ports, read back as inputs. a 2-byte read from the i/o ports (p0?7) of the max7325 returns the status of the eight i/o ports (as for a single-byte read), followed by the transition flags. again, the internal transition flags and the int output are cleared when the master acknowledges the slave address byte, yet the previous transition flag data is sent as the second byte. a 2-byte read from the push- pull ports of the max7325 repeatedly returns the status of the eight output ports, read back as inputs. a multibyte read (more than 2 bytes before the i 2 c stop bit) from the i/o ports (p0?7) of the max7325 repeatedly returns the port data, followed by the transi- tion flags. as the port data is resampled for each trans- mission, and the transition flags are reset each time, a multibyte read continuously returns the current data and identifies any changing input ports. scl sda by transmitter clock pulse for acknowledgement start condition sda by receiver 12 89 s figure 4. acknowledge sda scl a5 msb lsb ack a4 a1 a3 a0 a2 r/w figure 5. slave address
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 12 maxim integrated if a port input data change occurs during the read sequence, then int is reasserted during the i 2 c stop bit. the max7325 does not generate another interrupt during a single-byte or multibyte read. input port data is sampled during the preceding i 2 c acknowledge bit (the acknowledge bit for the i 2 c slave address in the case of a single-byte or two-byte read). a multibyte read from the push-pull ports of the max7325 repeatedly returns the status of the eight out- put ports, read back as inputs. a single-byte write to either port groups of the max7325 sets the logic state of all eight ports. a multibyte write to either port group of the max7325 repeatedly sets the logic state of all eight ports. reading the max7325 a read from the open-drain i/o ports of the max7325 starts with the master transmitting the port group? slave address with the r/ w bit set to high. the max7325 acknowledges the slave address, and sam- ples the ports during the acknowledge bit. int deasserts during the slave address acknowledge. typically, the master reads 1 or 2 bytes from the max7325, each byte being acknowledged by the mas- ter upon reception with the exception of the last byte. when the master reads one byte from the open-drain ports of the max7325 and subsequently issues a stop condition (figure 6), the max7325 transmits the current port data, clears the change flags, and resets the tran- sition detection. int deasserts during the slave scl max7325 slave address s1 1 0 a p 1 port t iv n p0 acknowledge from master acknowledge from max7325 p1 p2 p3 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 port i/o int output r/w port snapshot t ph t ir port snapshot s = start condition shaded = slave transmission p = stop condition n = not acknowledge t psu t ip int remains high until stop condition figure 6. reading open-drain ports of the max7325 (1 data byte)
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 13 maxim integrated scl max7325 slave address s110 a p 1 ports int output r/w port snapshot t iv t ph t ir a d0 d1 d2 d3 d4 d5 d6 d7 port snapshot t psu t ip d7 d6 d5 d4 d3 d2 d1 d0 n port snapshot int remains high until stop condition i0 i1 i2 i3 i4 i5 i6 i7 f0 f1 f2 f3 f4 f5 f6 f7 port inputs interrupt flags s = start condition shaded = slave transmission p = stop condition n = not acknowledge acknowledge from master acknowledge from max7325 figure 7. reading open-drain ports of the max7325 (2 data bytes) scl max7325 slave address sa p 1 acknowledge from max7325 port snapshot data port snapshot taken a p0 p1 p2 p3 data 1 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 port snapshot taken acknowledge from master r/w figure 8. reading push-pull ports of max7325 acknowledge. the new snapshot data is the current port data transmitted to the master, and therefore, port changes occuring during the transmission are detect- ed. int remains high until the stop condition. the master can read 2 bytes from the open-drain ports of the max7325 and subsequently issues a stop con- dition (figure 7). in this case, the max7325 transmits the current port data, followed by the change flags. the change flags are then cleared, and transition detection is reset. int goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowl- edge. the new snapshot data is the current port data transmitted to the master, and therefore, port changes occuring during the transmission are detected. int remains high until the stop condition. a read from the push-pull ports of the max7325 starts with the master transmitting the group? slave address with the r/ w bit set high. the max7325 acknowledges the slave address, and samples the logic state of the output ports during the acknowledge bit. the master can read one or more bytes from the push-pull ports of the max7325 and then issues a stop condition (figure 8). the max7325 transmits the current port data, read back from the actual port outputs (not the port output latches) during the acknowledge. if a port is forced to a logic state other than its programmed state, the read- back reflects this. if driving a capacitive load, the read- back port level verification algorithms may need to take the rc rise/fall time into account.
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 14 maxim integrated typically, the master reads one byte from the push-pull ports of the max7325, then issues a stop condition (figure 8). however, the master can read two or more bytes from the group b ports of the max7325, then issues a stop condition. in this case, the max7325 resamples the port outputs during each acknowledge and transmits the new data each time. writing the max7325 a write to either output port groups of the max7325 starts with the master transmitting the group? slave address with the r/ w bit set low. the max7325 acknowledges the slave address and samples the ports during the acknowledge bit. int goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowledge only when it writes to the open-drain ports. the master can now transmit one or more bytes of data. the max7325 acknowledges these subsequent bytes of data and updates the correspond- ing group? ports with each new byte until the master issues a stop condition (figure 9). applications information port input and i 2 c interface level translation from higher or lower logic voltages the max7325? sda, scl, ad0, ad2, rst , int , o8?15, and p0?7 are overvoltage protected to +6v. this allows the max7325 to operate from a lower supply voltage, such as +3.3v, while the i 2 c interface and/or any of the eight i/o ports are driven as inputs from a higher logic level, such as +5v. the max7325 can operate from a higher supply volt- age, such as +3v, while the i 2 c interface and/or some of the i/o ports p0?7 are driven from a lower logic level, such as +2.5v. for v+ < 1.8v, apply a minimum voltage of 0.8 x v+ to assert a logic-high on any input. for a v+ 1.8v, apply a voltage of 0.7 x v+ to assert a logic-high. for example, a max7325 operating from a +5v supply may not recognize a +3.3v nominal logic- high. one solution for input-level translation is to drive max7325 i/os from open-drain outputs. use a pullup resistor to v+ or a higher supply to ensure a high logic voltage greater than 0.7 x v+. port output signal-level translation the open-drain output architecture allows for level trans- lation to higher or lower voltages than the max7325? supply. use an external pullup resistor on any output to convert the high-impedance logic-high condition to a positive voltage level. the resistor can be connected to any voltage up to +6v, and the resistor value chosen to ensure no more than 20ma is sunk in the logic-low condi- tion. for interfacing cmos inputs, a pullup resistor value of 220k ? is a good starting point. use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. each of the push-pull output ports has protection diodes to v+ and gnd. when a port output is driven to a voltage higher than v+ or lower than gnd, the appro- priate protection diode clamps the output to a diode drop above v+ or below gnd. when the max7325 is powered down (v+ = 0v), every output port? protection scl sda slave address s0 12345678 aaa data 1 data 2 data to interrupt mask data to interrupt mask start condition r/w acknowledge from slave t pv data 2 valid data 1 valid internal write to port data out from port acknowledge from slave acknowledge from slave t pv figure 9. writing to the max7325
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 15 maxim integrated diodes to v+ and gnd continue to appear as a diode clamp from each output to gnd (figure 10). each of the i/o ports p0?7 has a protection diode to gnd (figure 11). when a port is driven to a voltage lower than gnd, the protection diode clamps the port to a diode drop below gnd. each of the i/o ports p0?7 also has a 40k ? (typ) pullup resistor that can be enabled or disabled. when a port input is driven to a voltage higher than v+, the body diode of the pullup enable switch conducts and the 40k ? pullup resistor is enabled. when the max7325 is powered down (v+ = 0v), each i/o port appears as a 40k ? resistor in series with a diode con- nected to 0v. input ports are protected to +6v under any of these circumstances (figure 11). driving led loads when driving leds from one of the outputs, a resistor must be fitted in series with the led to limit the led current to no more than 20ma. connect the led cath- ode to the max7325 port, and the led anode to v+ through the series current-limiting resistor, r led . set the port output low to illuminate the led. choose the resistor value according to the following formula: r led = (v supply - v led - v ol ) / i led where: r led is the resistance of the resistor in series with the led ( ? ). v supply is the supply voltage used to drive the led (v). v led is the forward voltage of the led (v). v ol is the output low voltage of the max7325 when sinking i led (v). i led is the desired operating current of the led (a). for example, to operate a 2.2v red led at 10ma from a +5v supply: r led = (5 - 2.2 - 0.1) / 0.01 = 270 ? driving load currents higher than 20ma the max7325 can be used to drive loads, such as relays that draw more than 20ma, by paralleling outputs. use at least one output per 20ma of load current; for example, a 5v 330mw relay draws 66ma, and therefore, requires four paralleled outputs. any combination of outputs can be used as part of a load-sharing design because any combination of ports can be set or cleared at the same time by writing to the max7325. do not exceed a total sink current of 100ma for the device. the max7325 must be protected from the negative- voltage transient generated when switching off induc- tive loads (such as relays), by connecting a reverse-biased diode across the inductive load. choose the peak current for the diode to be greater than the inductive load? operating current. power-supply considerations the max7325 operates with a supply voltage of +1.71v to +5.5v. bypass the supply to gnd with a ceramic capacitor of at least 0.047? as close as possible to the device. for the tqfn version, additionally connect the exposed pad to gnd. p0?p7 pullup enable input output 40k ? max7325 v+ v+ figure 11. max7325 open-drain i/o port structure output v+ gnd gnd v+ o8?o15 max7325 figure 10. max7325 push-pull output port structure
max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os 16 maxim integrated top view 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 int v+ sda scl ad0 o15 o14 o13 o12 max7325 qsop + rst ad2 p2 p0 p1 p3 p4 16 15 9 10 o11 o10 p5 p6 14 13 11 12 o9 o8 p7 gnd pin configurations (continued) max7325 p2 p7 p6 p5 p4 o11 o10 o9 o8 o15 o14 o13 o12 v+ 3.3v c scl scl sda ad0 p1 p0 sda p3 gnd ad2 int output output output output rst int rst input/output input/output input/output input/output input/output input/output input/output input/output typical application circuit i 2 c control o9 o8 o11 o10 o12 o13 o14 o15 p1 p0 p3 p2 p4 p5 p6 p7 int i/o ports power- on reset input filter rst sda scl ad2 ad0 max7325 functional diagram chip information process: bicmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 qsop e24+1 21-0055 90-0172 24 tqfn-ep t2444+4 21-0139 90-0022
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time . the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 17 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products , inc. max7325 i 2 c port expander with 8 push-pull and 8 open-drain i/os revision history revision number revision date description pages changed 0 9/06 initial release 1 9/12 added the max7325aeg/v+ to the ordering information 1

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